296 lines
7.5 KiB
C
296 lines
7.5 KiB
C
// Copyright 2017 Google LLC
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// Copyright 2020 Intel Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
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#include "cpu_features_cache_info.h"
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#include "cpu_features_macros.h"
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CPU_FEATURES_START_CPP_NAMESPACE
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// CPUID Vendors
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#define CPU_FEATURES_VENDOR_GENUINE_INTEL "GenuineIntel"
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#define CPU_FEATURES_VENDOR_AUTHENTIC_AMD "AuthenticAMD"
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#define CPU_FEATURES_VENDOR_HYGON_GENUINE "HygonGenuine"
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#define CPU_FEATURES_VENDOR_CENTAUR_HAULS "CentaurHauls"
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#define CPU_FEATURES_VENDOR_SHANGHAI " Shanghai "
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// See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features.
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// The field names are based on the short name provided in the wikipedia tables.
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typedef struct {
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int fpu : 1;
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int tsc : 1;
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int cx8 : 1;
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int clfsh : 1;
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int mmx : 1;
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int aes : 1;
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int erms : 1;
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int f16c : 1;
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int fma4 : 1;
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int fma3 : 1;
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int vaes : 1;
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int vpclmulqdq : 1;
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int bmi1 : 1;
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int hle : 1;
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int bmi2 : 1;
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int rtm : 1;
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int rdseed : 1;
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int clflushopt : 1;
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int clwb : 1;
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int sse : 1;
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int sse2 : 1;
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int sse3 : 1;
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int ssse3 : 1;
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int sse4_1 : 1;
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int sse4_2 : 1;
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int sse4a : 1;
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int avx : 1;
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int avx_vnni : 1;
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int avx2 : 1;
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int avx512f : 1;
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int avx512cd : 1;
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int avx512er : 1;
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int avx512pf : 1;
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int avx512bw : 1;
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int avx512dq : 1;
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int avx512vl : 1;
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int avx512ifma : 1;
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int avx512vbmi : 1;
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int avx512vbmi2 : 1;
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int avx512vnni : 1;
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int avx512bitalg : 1;
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int avx512vpopcntdq : 1;
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int avx512_4vnniw : 1;
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int avx512_4vbmi2 : 1; // Note: this is an alias to avx512_4fmaps.
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int avx512_second_fma : 1;
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int avx512_4fmaps : 1;
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int avx512_bf16 : 1;
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int avx512_vp2intersect : 1;
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int avx512_fp16 : 1;
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int amx_bf16 : 1;
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int amx_tile : 1;
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int amx_int8 : 1;
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int amx_fp16 : 1;
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int pclmulqdq : 1;
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int smx : 1;
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int sgx : 1;
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int cx16 : 1; // aka. CMPXCHG16B
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int sha : 1;
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int popcnt : 1;
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int movbe : 1;
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int rdrnd : 1;
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int dca : 1;
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int ss : 1;
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int adx : 1;
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int lzcnt : 1; // Note: this flag is called ABM for AMD, LZCNT for Intel.
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int gfni : 1;
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int movdiri : 1;
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int movdir64b : 1;
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int fs_rep_mov : 1; // Fast short REP MOV
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int fz_rep_movsb : 1; // Fast zero-length REP MOVSB
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int fs_rep_stosb : 1; // Fast short REP STOSB
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int fs_rep_cmpsb_scasb : 1; // Fast short REP CMPSB/SCASB
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int lam: 1; // Intel Linear Address Mask
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int uai: 1; // AMD Upper Address Ignore
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// Make sure to update X86FeaturesEnum below if you add a field here.
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} X86Features;
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typedef struct {
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X86Features features;
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int family;
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int model;
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int stepping;
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char vendor[13]; // 0 terminated string
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char brand_string[49]; // 0 terminated string
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} X86Info;
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// Calls cpuid and returns an initialized X86info.
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X86Info GetX86Info(void);
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// Returns cache hierarchy informations.
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// Can call cpuid multiple times.
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CacheInfo GetX86CacheInfo(void);
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typedef enum {
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X86_UNKNOWN,
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ZHAOXIN_ZHANGJIANG, // ZhangJiang
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ZHAOXIN_WUDAOKOU, // WuDaoKou
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ZHAOXIN_LUJIAZUI, // LuJiaZui
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ZHAOXIN_YONGFENG, // YongFeng
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INTEL_80486, // 80486
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INTEL_P5, // P5
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INTEL_LAKEMONT, // LAKEMONT
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INTEL_CORE, // CORE
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INTEL_PNR, // PENRYN
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INTEL_NHM, // NEHALEM
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INTEL_ATOM_BNL, // BONNELL
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INTEL_WSM, // WESTMERE
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INTEL_SNB, // SANDYBRIDGE
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INTEL_IVB, // IVYBRIDGE
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INTEL_ATOM_SMT, // SILVERMONT
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INTEL_HSW, // HASWELL
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INTEL_BDW, // BROADWELL
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INTEL_SKL, // SKYLAKE
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INTEL_CCL, // CASCADELAKE
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INTEL_ATOM_GMT, // GOLDMONT
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INTEL_ATOM_GMT_PLUS, // GOLDMONT+
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INTEL_ATOM_TMT, // TREMONT
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INTEL_KBL, // KABY LAKE
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INTEL_CFL, // COFFEE LAKE
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INTEL_WHL, // WHISKEY LAKE
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INTEL_CML, // COMET LAKE
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INTEL_CNL, // CANNON LAKE
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INTEL_ICL, // ICE LAKE
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INTEL_TGL, // TIGER LAKE
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INTEL_SPR, // SAPPHIRE RAPIDS
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INTEL_ADL, // ALDER LAKE
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INTEL_RCL, // ROCKET LAKE
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INTEL_RPL, // RAPTOR LAKE
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INTEL_KNIGHTS_M, // KNIGHTS MILL
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INTEL_KNIGHTS_L, // KNIGHTS LANDING
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INTEL_KNIGHTS_F, // KNIGHTS FERRY
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INTEL_KNIGHTS_C, // KNIGHTS CORNER
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INTEL_NETBURST, // NETBURST
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AMD_HAMMER, // K8 HAMMER
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AMD_K10, // K10
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AMD_K11, // K11
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AMD_K12, // K12 LLANO
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AMD_BOBCAT, // K14 BOBCAT
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AMD_PILEDRIVER, // K15 PILEDRIVER
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AMD_STREAMROLLER, // K15 STREAMROLLER
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AMD_EXCAVATOR, // K15 EXCAVATOR
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AMD_BULLDOZER, // K15 BULLDOZER
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AMD_JAGUAR, // K16 JAGUAR
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AMD_PUMA, // K16 PUMA
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AMD_ZEN, // K17 ZEN
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AMD_ZEN_PLUS, // K17 ZEN+
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AMD_ZEN2, // K17 ZEN 2
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AMD_ZEN3, // K19 ZEN 3
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AMD_ZEN4, // K19 ZEN 4
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X86_MICROARCHITECTURE_LAST_,
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} X86Microarchitecture;
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// Returns the underlying microarchitecture by looking at X86Info's vendor,
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// family and model.
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X86Microarchitecture GetX86Microarchitecture(const X86Info* info);
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// Calls cpuid and fills the brand_string.
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// - brand_string *must* be of size 49 (beware of array decaying).
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// - brand_string will be zero terminated.
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CPU_FEATURES_DEPRECATED("brand_string is now embedded in X86Info by default")
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void FillX86BrandString(char brand_string[49]);
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////////////////////////////////////////////////////////////////////////////////
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// Introspection functions
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typedef enum {
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X86_FPU,
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X86_TSC,
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X86_CX8,
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X86_CLFSH,
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X86_MMX,
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X86_AES,
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X86_ERMS,
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X86_F16C,
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X86_FMA4,
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X86_FMA3,
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X86_VAES,
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X86_VPCLMULQDQ,
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X86_BMI1,
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X86_HLE,
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X86_BMI2,
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X86_RTM,
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X86_RDSEED,
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X86_CLFLUSHOPT,
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X86_CLWB,
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X86_SSE,
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X86_SSE2,
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X86_SSE3,
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X86_SSSE3,
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X86_SSE4_1,
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X86_SSE4_2,
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X86_SSE4A,
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X86_AVX,
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X86_AVX_VNNI,
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X86_AVX2,
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X86_AVX512F,
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X86_AVX512CD,
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X86_AVX512ER,
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X86_AVX512PF,
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X86_AVX512BW,
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X86_AVX512DQ,
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X86_AVX512VL,
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X86_AVX512IFMA,
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X86_AVX512VBMI,
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X86_AVX512VBMI2,
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X86_AVX512VNNI,
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X86_AVX512BITALG,
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X86_AVX512VPOPCNTDQ,
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X86_AVX512_4VNNIW,
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X86_AVX512_4VBMI2, // Note: this is an alias to X86_AVX512_4FMAPS.
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X86_AVX512_SECOND_FMA,
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X86_AVX512_4FMAPS,
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X86_AVX512_BF16,
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X86_AVX512_VP2INTERSECT,
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X86_AVX512_FP16,
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X86_AMX_BF16,
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X86_AMX_TILE,
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X86_AMX_INT8,
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X86_AMX_FP16,
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X86_PCLMULQDQ,
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X86_SMX,
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X86_SGX,
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X86_CX16,
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X86_SHA,
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X86_POPCNT,
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X86_MOVBE,
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X86_RDRND,
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X86_DCA,
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X86_SS,
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X86_ADX,
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X86_LZCNT,
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X86_GFNI,
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X86_MOVDIRI,
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X86_MOVDIR64B,
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X86_FS_REP_MOV,
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X86_FZ_REP_MOVSB,
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X86_FS_REP_STOSB,
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X86_FS_REP_CMPSB_SCASB,
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X86_LAM,
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X86_UAI,
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X86_LAST_,
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} X86FeaturesEnum;
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int GetX86FeaturesEnumValue(const X86Features* features, X86FeaturesEnum value);
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const char* GetX86FeaturesEnumName(X86FeaturesEnum);
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const char* GetX86MicroarchitectureName(X86Microarchitecture);
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CPU_FEATURES_END_CPP_NAMESPACE
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#if !defined(CPU_FEATURES_ARCH_X86)
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#error "Including cpuinfo_x86.h from a non-x86 target."
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#endif
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#endif // CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
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