302 lines
12 KiB
C
302 lines
12 KiB
C
// Copyright 2017 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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////////////////////////////////////////////////////////////////////////////////
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// A note on Windows AArch64 implementation
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////////////////////////////////////////////////////////////////////////////////
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// Getting cpu info via EL1 system registers is not possible, so we delegate it
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// to the Windows API (i.e., IsProcessorFeaturePresent and GetNativeSystemInfo).
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// The `implementer`, `variant` and `part` fields of the `Aarch64Info` struct
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// are not used, so they are set to 0. To get `revision` we use
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// `wProcessorRevision` from `SYSTEM_INFO`.
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//
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// Cryptographic Extension:
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// -----------------------------------------------------------------------------
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// According to documentation Arm Architecture Reference Manual for
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// A-profile architecture. A2.3 The Armv8 Cryptographic Extension. The Armv8.0
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// Cryptographic Extension provides instructions for the acceleration of
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// encryption and decryption, and includes the following features: FEAT_AES,
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// FEAT_PMULL, FEAT_SHA1, FEAT_SHA256.
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// see: https://developer.arm.com/documentation/ddi0487/latest
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//
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// We use `PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE` to detect all Armv8.0 crypto
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// features. This value reports all features or nothing, so even if you only
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// have support FEAT_AES and FEAT_PMULL, it will still return false.
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//
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// From Armv8.2, an implementation of the Armv8.0 Cryptographic Extension can
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// include either or both of:
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//
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// • The AES functionality, including support for multiplication of 64-bit
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// polynomials. The ID_AA64ISAR0_EL1.AES field indicates whether this
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// functionality is supported.
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// • The SHA1 and SHA2-256 functionality. The ID_AA64ISAR0_EL1.{SHA2, SHA1}
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// fields indicate whether this functionality is supported.
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//
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// ID_AA64ISAR0_EL1.AES, bits [7:4]:
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// Indicates support for AES instructions in AArch64 state. Defined values are:
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// - 0b0000 No AES instructions implemented.
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// - 0b0001 AESE, AESD, AESMC, and AESIMC instructions implemented.
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// - 0b0010 As for 0b0001, plus PMULL/PMULL2 instructions operating on 64-bit
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// data quantities.
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//
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// FEAT_AES implements the functionality identified by the value 0b0001.
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// FEAT_PMULL implements the functionality identified by the value 0b0010.
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// From Armv8, the permitted values are 0b0000 and 0b0010.
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//
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// ID_AA64ISAR0_EL1.SHA1, bits [11:8]:
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// Indicates support for SHA1 instructions in AArch64 state. Defined values are:
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// - 0b0000 No SHA1 instructions implemented.
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// - 0b0001 SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions
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// implemented.
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//
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// FEAT_SHA1 implements the functionality identified by the value 0b0001.
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// From Armv8, the permitted values are 0b0000 and 0b0001.
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// If the value of ID_AA64ISAR0_EL1.SHA2 is 0b0000, this field must have the
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// value 0b0000.
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//
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// ID_AA64ISAR0_EL1.SHA2, bits [15:12]:
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// Indicates support for SHA2 instructions in AArch64 state. Defined values are:
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// - 0b0000 No SHA2 instructions implemented.
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// - 0b0001 Implements instructions: SHA256H, SHA256H2, SHA256SU0, and
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// SHA256SU1.
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// - 0b0010 Implements instructions:
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// • SHA256H, SHA256H2, SHA256SU0, and SHA256SU1.
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// • SHA512H, SHA512H2, SHA512SU0, and SHA512SU1.
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//
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// FEAT_SHA256 implements the functionality identified by the value 0b0001.
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// FEAT_SHA512 implements the functionality identified by the value 0b0010.
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//
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// In Armv8, the permitted values are 0b0000 and 0b0001.
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// From Armv8.2, the permitted values are 0b0000, 0b0001, and 0b0010.
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//
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// If the value of ID_AA64ISAR0_EL1.SHA1 is 0b0000, this field must have the
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// value 0b0000.
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//
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// If the value of this field is 0b0010, ID_AA64ISAR0_EL1.SHA3
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// must have the value 0b0001.
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//
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// Other cryptographic features that we cannot detect such as sha512, sha3, sm3,
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// sm4, sveaes, svepmull, svesha3, svesm4 we set to 0.
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//
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// FP/SIMD:
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// -----------------------------------------------------------------------------
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// FP/SIMD must be implemented on all Armv8.0 implementations, but
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// implementations targeting specialized markets may support the following
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// combinations:
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//
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// • No NEON or floating-point.
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// • Full floating-point and SIMD support with exception trapping.
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// • Full floating-point and SIMD support without exception trapping.
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//
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// ref:
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// https://developer.arm.com/documentation/den0024/a/AArch64-Floating-point-and-NEON
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//
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// So, we use `PF_ARM_VFP_32_REGISTERS_AVAILABLE`,
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// `PF_ARM_NEON_INSTRUCTIONS_AVAILABLE` to detect `asimd` and `fp`
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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#include "cpu_features_cache_info.h"
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#include "cpu_features_macros.h"
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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int fp : 1; // Floating-point.
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int asimd : 1; // Advanced SIMD.
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int evtstrm : 1; // Generic timer generated events.
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int aes : 1; // Hardware-accelerated Advanced Encryption Standard.
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int pmull : 1; // Polynomial multiply long.
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int sha1 : 1; // Hardware-accelerated SHA1.
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int sha2 : 1; // Hardware-accelerated SHA2-256.
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int crc32 : 1; // Hardware-accelerated CRC-32.
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int atomics : 1; // Armv8.1 atomic instructions.
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int fphp : 1; // Half-precision floating point support.
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int asimdhp : 1; // Advanced SIMD half-precision support.
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int cpuid : 1; // Access to certain ID registers.
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int asimdrdm : 1; // Rounding Double Multiply Accumulate/Subtract.
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int jscvt : 1; // Support for JavaScript conversion.
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int fcma : 1; // Floating point complex numbers.
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int lrcpc : 1; // Support for weaker release consistency.
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int dcpop : 1; // Data persistence writeback.
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int sha3 : 1; // Hardware-accelerated SHA3.
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int sm3 : 1; // Hardware-accelerated SM3.
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int sm4 : 1; // Hardware-accelerated SM4.
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int asimddp : 1; // Dot product instruction.
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int sha512 : 1; // Hardware-accelerated SHA512.
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int sve : 1; // Scalable Vector Extension.
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int asimdfhm : 1; // Additional half-precision instructions.
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int dit : 1; // Data independent timing.
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int uscat : 1; // Unaligned atomics support.
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int ilrcpc : 1; // Additional support for weaker release consistency.
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int flagm : 1; // Flag manipulation instructions.
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int ssbs : 1; // Speculative Store Bypass Safe PSTATE bit.
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int sb : 1; // Speculation barrier.
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int paca : 1; // Address authentication.
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int pacg : 1; // Generic authentication.
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int dcpodp : 1; // Data cache clean to point of persistence.
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int sve2 : 1; // Scalable Vector Extension (version 2).
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int sveaes : 1; // SVE AES instructions.
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int svepmull : 1; // SVE polynomial multiply long instructions.
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int svebitperm : 1; // SVE bit permute instructions.
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int svesha3 : 1; // SVE SHA3 instructions.
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int svesm4 : 1; // SVE SM4 instructions.
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int flagm2 : 1; // Additional flag manipulation instructions.
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int frint : 1; // Floating point to integer rounding.
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int svei8mm : 1; // SVE Int8 matrix multiplication instructions.
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int svef32mm : 1; // SVE FP32 matrix multiplication instruction.
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int svef64mm : 1; // SVE FP64 matrix multiplication instructions.
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int svebf16 : 1; // SVE BFloat16 instructions.
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int i8mm : 1; // Int8 matrix multiplication instructions.
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int bf16 : 1; // BFloat16 instructions.
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int dgh : 1; // Data Gathering Hint instruction.
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int rng : 1; // True random number generator support.
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int bti : 1; // Branch target identification.
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int mte : 1; // Memory tagging extension.
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int ecv : 1; // Enhanced counter virtualization.
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int afp : 1; // Alternate floating-point behaviour.
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int rpres : 1; // 12-bit reciprocal (square root) estimate precision.
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int mte3 : 1; // MTE asymmetric fault handling.
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int sme : 1; // Scalable Matrix Extension.
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int smei16i64 : 1; // 16-bit to 64-bit integer widening outer product.
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int smef64f64 : 1; // FP64 to FP64 outer product.
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int smei8i32 : 1; // 8-bit to 32-bit integer widening outer product.
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int smef16f32 : 1; // FP16 to FP32 outer product.
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int smeb16f32 : 1; // BFloat16 to FP32 outper product.
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int smef32f32 : 1; // FP32 to FP32 outer product.
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int smefa64 : 1; // Full A64 support for SME in streaming mode.
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int wfxt : 1; // WFE and WFI with timeout.
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int ebf16 : 1; // Extended BFloat16 instructions.
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int sveebf16 : 1; // SVE BFloat16 instructions.
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int cssc : 1; // Common short sequence compression instructions.
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int rprfm : 1; // Range Prefetch Memory hint instruction.
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int sve2p1 : 1; // Scalable Vector Extension (version 2.1).
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int sme2 : 1; // Scalable Matrix Extension (version 2).
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int sme2p1 : 1; // Scalable Matrix Extension (version 2.1).
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int smei16i32 : 1; // 16-bit to 64-bit integer widening outer product.
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int smebi32i32 : 1; // 1-bit binary to 32-bit integer outer product.
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int smeb16b16 : 1; // SME2.1 BFloat16 instructions.
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int smef16f16 : 1; // FP16 to FP16 outer product.
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// Make sure to update Aarch64FeaturesEnum below if you add a field here.
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} Aarch64Features;
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typedef struct {
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Aarch64Features features;
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int implementer; // We set 0 for Windows.
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int variant; // We set 0 for Windows.
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int part; // We set 0 for Windows.
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int revision; // We use GetNativeSystemInfo to get processor revision for
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// Windows.
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} Aarch64Info;
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Aarch64Info GetAarch64Info(void);
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////////////////////////////////////////////////////////////////////////////////
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// Introspection functions
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typedef enum {
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AARCH64_FP,
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AARCH64_ASIMD,
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AARCH64_EVTSTRM,
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AARCH64_AES,
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AARCH64_PMULL,
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AARCH64_SHA1,
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AARCH64_SHA2,
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AARCH64_CRC32,
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AARCH64_ATOMICS,
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AARCH64_FPHP,
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AARCH64_ASIMDHP,
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AARCH64_CPUID,
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AARCH64_ASIMDRDM,
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AARCH64_JSCVT,
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AARCH64_FCMA,
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AARCH64_LRCPC,
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AARCH64_DCPOP,
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AARCH64_SHA3,
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AARCH64_SM3,
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AARCH64_SM4,
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AARCH64_ASIMDDP,
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AARCH64_SHA512,
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AARCH64_SVE,
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AARCH64_ASIMDFHM,
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AARCH64_DIT,
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AARCH64_USCAT,
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AARCH64_ILRCPC,
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AARCH64_FLAGM,
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AARCH64_SSBS,
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AARCH64_SB,
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AARCH64_PACA,
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AARCH64_PACG,
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AARCH64_DCPODP,
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AARCH64_SVE2,
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AARCH64_SVEAES,
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AARCH64_SVEPMULL,
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AARCH64_SVEBITPERM,
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AARCH64_SVESHA3,
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AARCH64_SVESM4,
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AARCH64_FLAGM2,
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AARCH64_FRINT,
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AARCH64_SVEI8MM,
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AARCH64_SVEF32MM,
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AARCH64_SVEF64MM,
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AARCH64_SVEBF16,
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AARCH64_I8MM,
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AARCH64_BF16,
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AARCH64_DGH,
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AARCH64_RNG,
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AARCH64_BTI,
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AARCH64_MTE,
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AARCH64_ECV,
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AARCH64_AFP,
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AARCH64_RPRES,
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AARCH64_MTE3,
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AARCH64_SME,
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AARCH64_SME_I16I64,
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AARCH64_SME_F64F64,
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AARCH64_SME_I8I32,
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AARCH64_SME_F16F32,
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AARCH64_SME_B16F32,
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AARCH64_SME_F32F32,
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AARCH64_SME_FA64,
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AARCH64_WFXT,
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AARCH64_EBF16,
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AARCH64_SVE_EBF16,
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AARCH64_CSSC,
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AARCH64_RPRFM,
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AARCH64_SVE2P1,
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AARCH64_SME2,
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AARCH64_SME2P1,
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AARCH64_SME_I16I32,
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AARCH64_SME_BI32I32,
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AARCH64_SME_B16B16,
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AARCH64_SME_F16F16,
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AARCH64_LAST_,
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} Aarch64FeaturesEnum;
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int GetAarch64FeaturesEnumValue(const Aarch64Features* features,
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Aarch64FeaturesEnum value);
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const char* GetAarch64FeaturesEnumName(Aarch64FeaturesEnum);
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CPU_FEATURES_END_CPP_NAMESPACE
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#if !defined(CPU_FEATURES_ARCH_AARCH64)
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#error "Including cpuinfo_aarch64.h from a non-aarch64 target."
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#endif
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#endif // CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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